Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then “wired,” or interconnected, together to define a specific electric circuit, such as a computer memory.
Interconnecting millions of microscopic components typically entails covering the components with an insulative layer, etching small holes in the insulative layer to expose portions of the components underneath, and digging trenches in the layer to define a wiring pattern. Then, through metallization, the holes and trenches are filled with metal to form line-like wires between the components. The wires are typically about one micron thick, or about 100 times thinner than a human hair.
Aluminum and its alloys with silicon and copper are the most common metals used for the wires, or interconnects. However, at sub-micron dimensions, that is, dimensions appreciable less than one micron, aluminum-based interconnections present not only higher electrical resistances which waste power and slows down the integrated circuit, but also poor electromigration resistance which lets the aluminum diffuse, or leach, into neighboring structures. This diffusion degrades performance of an integrated circuit, ultimately undermining its reliability. Thus, there is a need to form sub-micron interconnections from metals other than aluminum.
Copper appears, because of its lower electrical resistivity and higher electromigration resistance, to be a promising substitute for aluminum. However, conventional interconnection techniques have proven impractical for making sub-micron interconnects from copper, specifically for filling the quarter-micron-wide holes and trenches thought necessary for tomorrow's smaller, more densely-packed integrated circuits.
For example, when using the conventional metallization technique of sputtering to fill trenches with copper, copper atoms spray out widely (in comparison to the width of the trenches), stick to the sidewalls of the trenches, and then to each other, eventually building bridges, or closures, across a trench and ultimately leaving voids, or wormholes, in the resulting copper wire. Similarly, when sputter-filling small holes with copper, the resulting vias are riddled with voids. These voids not only reduce the physical integrity of the copper interconnects, but also increase their electrical resistance significantly.
One attempt at solving this problem is the Hirao technique disclosed by S. Hirao and his coworkers in their article “A Novel Copper Reflow Process Using Dual Wetting Layers” (Symposium on VLSI Technology, Digest of Technical Papers, pp. 57-58 (1997)). The Hirao technique forms a trench and two diffusion barriers, one inside the trench and the other outside the trench. The inside diffusion barrier consists of a high-wetting, titanium-tungsten, and the outside diffusion barrier consists of a low-wetting, silicon-nitride. Next, the Hirao technique conventionally sputter deposits copper over both the inside and outside diffusion barriers, and afterward executes a reflow step, which heats the copper to 450° C. for 5 minutes in a vacuum. During reflow, the copper flows off the low-wetting, outside diffusion barrier into the trench, where the high-wetting diffusion barrier, to which copper easily sticks, promotes voidless copper consolidation.
Unfortunately, the Hirao technique suffers from at least four drawbacks. First, the technique is time-consuming and inefficient, particularly during formation of the outside diffusion barrier. Forming the outside diffusion barrier entails depositing a sheet of silicon nitride on an insulative layer and then masking and etching through the barrier into the insulative layer to form the trench. This etching is especially time consuming because it must dissolve not only the silicon nitride but also the insulative layer. Second, the Hirao technique forms the inside diffusion barrier using conventional sputtering which fails to yield a lining that conforms accurately to the profile of the trench or hole, ultimately yielding a deformed copper conductor with a smaller cross-section and therefore greater resistance. Third, conventional sputtering deposits the inside barrier material both inside and outside the trench, necessitating an additional scrubbing or polishing step to remove the material outside the trench. Not only is this additional scrubbing step time consuming, but it very likely wears away some of the silicon nitride material forming the outside barrier layer, reducing its effectiveness. Fourth, to control wettability of the barrier layers, the Hirao technique describes an argon-plasma treatment, another time-consuming step that further impairs its practicality.
Accordingly, there remains a need for practical methods of making low-resistance, high-reliability copper interconnections.